Sandisk And SK Hynix Open HBF Spec For AI Memory Capacity
Tom’s Hardware put Sandisk and SK hynix’s OCP High Bandwidth Flash specification at up to 512GB per package, with bandwidth grades reaching 3.0 TB/s for AI inference systems.
Sandisk and SK hynix have moved High Bandwidth Flash from a joint concept into an Open Compute Project specification, giving AI inference system designers a proposed memory tier between high-capacity NAND and lower-capacity HBM, according to Tom’s Hardware.
The specification targets a problem that GPU suppliers and cloud operators keep encountering as inference models grow: memory capacity near the accelerator can matter as much as raw compute.
HBF is pitched as non-volatile NAND-based storage with bandwidth closer to high-bandwidth memory, not as a direct replacement for HBM in every workload.
HBF Raises The Capacity Target
According to Tom’s Hardware, the initial HBF specification defines package capacity at up to 512GB and allows 8-Hi or 16-Hi NAND stack arrangements.
Sandisk’s earlier HBF core-die terminology records the core design point: these are specialized fast-interface components, not ordinary 3D NAND stacks.
The capacity comparison with HBM4 explains the proposed role.
HBF is designed for inference workloads that need a larger local memory pool, so the trade-off becomes capacity and persistence against HBM’s latency advantage.
Bandwidth And Interface Claims Remain Early
According to Tom’s Hardware, HBF performance spans about 0.4 TB/s to 3.0 TB/s across three grades.
Its comparison with a single HBM4 stack leaves two limits in view: the HBF number may describe a subsystem instead of one package, and latency is still expected to favor HBM4.
The integration path is also not fully settled in the public record.
SK hynix identifies UCIe as the interconnect for heterogeneous computing platforms, while Sandisk refers to an xPU-HBF interface that could map to UCIe implementations from companies such as Broadcom or Marvell.
Adoption Is The Commercial Test
The published specification covers electrical and interface characteristics, packaging and reliability guidelines, and software I/O requirements for stacked HBF devices.
Detailed OCP documents remain outside the public release for now.
The engineering burden sits in the base die and interface.
Extracting very high bandwidth from a dense HBF package requires concurrent array access and a complex interface base die, so package capacity alone does not settle the accelerator-design question.
Market support remains narrow for now.
Google and Tenstorrent have expressed interest in the HBF consortium since the Sandisk-SK hynix collaboration was announced in 2025, while other major chip and memory companies listed in the account have not.
The specification now gives accelerator designers a common target, but broad adoption still depends on whether system builders accept another memory tier in the AI inference stack.
