Marvell Warrant Ties Google TPU Chip Supply To $120 Billion Revenue Path
Tech Wire Asia reported that Google and Marvell signed a July 29 agreement covering custom TPU ecosystem silicon, with most warrant shares vesting through purchase-linked tranches tied to as much as $120 billion in product revenue.
Google has widened Marvell Technology's place in the chip stack around its tensor processing units, Tech Wire Asia reported, with an August 19 Marvell filing showing a July 29 commercial agreement that covers accelerator, storage, networking and memory-related silicon.
The contract is tied to Google's TPU ecosystem rather than to one named processor generation.
Its product list includes custom AI inference accelerators, controllers for storage, network-interface chips, memory-interface chips and near-memory computing parts.
That mix places Marvell in the systems surrounding Google's TPU clusters as well as in inference silicon.
Near-memory computing moves some work closer to memory, cutting the traffic that would otherwise pass back and forth between memory and processors.
The filing leaves product placement open.
No current or future TPU generation is matched to a particular Marvell component, and the disclosed language only links the programs to the broader TPU platform.
A share warrant turns the supply agreement into a long purchase-linked arrangement.
Marvell gave Google the right to acquire as many as 58.97 million Marvell shares at $206.58 a share, which would put a full exercise near $12.18 billion.
The first-year portion is small: 1.36 million shares vest through equal quarterly instalments.
The rest depends on buying activity by Google and its affiliates from Marvell's fiscal third quarter of 2027 through fiscal 2033.
Marvell split that larger pool into 240 equal pieces.
Each piece vests after $500 million of revenue from the custom products, so the complete purchase-linked schedule maps to $120 billion of revenue.
The warrant can be exercised until August 18, 2033 if the conditions are met.
The announcement moved chip shares in different directions.
Marvell rose nearly 8%, Alphabet was little changed and Broadcom dropped more than 5%; Broadcom already has a separate Google agreement this year covering future TPU development and supply, networking and other components for next-generation AI racks.
Google's own TPU roadmap explains why the surrounding components matter.
TPU 8t is built mainly for large-scale training, TPU 8i is aimed at inference and reinforcement-learning workloads, and a TPU 8t superpod can reach 9,600 chips.
The AI Hypercomputer design combines accelerators, networking, storage and software.
In TPU 8t systems, TPUDirect RDMA and TPUDirect Storage move data more directly among TPU memory, network interfaces and storage, reducing some host-CPU involvement in those transfers.
The Marvell agreement does not settle how Google will divide future work among suppliers.
Marvell and Broadcom disclosures do not allocate TPU programs or order volumes, and Google Cloud still offers Nvidia hardware next to Google's own accelerators.
Custom processors now sit beside external chip suppliers across the hyperscaler market.
AWS uses Trainium, Microsoft runs Maia processors, Meta is expanding MTIA, and Google's new Marvell arrangement adds another supplier to the memory, networking, storage and inference layers around TPU infrastructure.
