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Arm Neoverse CSS N4 Sets 3nm Base For Future DPUs And Servers

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Arm introduced the Neoverse CSS N4 compute subsystem, pairing up to 128 cores with CMN S4, faster memory options and PCIe Gen7 for future infrastructure chips.

Verified against source materialEdited by SendTech Times Chips & Compute DeskSource: ServeTheHome
Arm Neoverse CSS N4 Sets 3nm Base For Future DPUs And Servers
Image source: ServeTheHome

Arm has introduced the Neoverse CSS N4 compute subsystem for future server, DPU and network-appliance chips, giving infrastructure silicon teams a 3nm platform with up to 128 cores, ServeTheHome wrote.

The launch matters less as a finished processor than as a reusable base for companies building their own chips.

Neoverse CSS gives customers a pre-integrated Arm compute subsystem, so a vendor can start from Arm’s CPU, interconnect and platform work instead of assembling every block independently.

CSS N4 is built around Neoverse N4 cores and makes Armv9.3 the baseline architecture.

The design spans from 8 to 128 cores per die and is aimed at power-efficient compute with operating frequencies of up to 3.8GHz.

Support for FP8 and MMLA adds a machine-learning and matrix-math angle to a core family that is often used outside headline server CPUs.

The interconnect is a central part of the design.

Arm’s Neoverse CMN S4 fabric can scale to a 16-by-16 mesh and supports coherent multi-chiplet links through CHI C2C.

That fabric is what ties cores, memory controllers, I/O and die-to-die interfaces together, making the subsystem relevant for chiplet-era infrastructure designs rather than only monolithic processors.

The memory and I/O choices point to products that are still ahead of the current market cycle.

CSS N4 supports LPDDR6, DDR5 and MRDIMMs running at 8000 to 12000MT/s.

CSS N4 also supports up to 128 lanes of PCIe Gen7.

A recent XSight Labs design shows why the CSS route can appeal to smaller infrastructure-chip companies.

Its E1 DPU uses an older Neoverse CSS N2 base with 64 Neoverse N2 cores for an 800G data-processing unit.

For a startup, the point is not only the Arm instruction set; the shared subsystem can shorten the path from design work to a marketable networking or DPU product.

Arm’s V-series cores often draw more attention in high-performance server discussions, and Arm is also building its own AGI CPU with Neoverse V3 cores.

CSS N4 extends the N-series path that has become common in DPUs and network appliances, with more detail expected as customers move the new IP toward actual silicon.

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