Astera Labs Pushes Leo Memory Controllers Into DDR4 Reuse And AI Fabrics

Astera Labs has released three new Leo smart memory controllers as data-center operators look for cheaper ways to expand memory during DDR5 shortages, ServeTheHome reported.

The announcement puts CXL memory expansion into a market test that is no longer only about adding capacity.

Leo 2 updates Astera’s CPU-attached controller family for newer server platforms, while Leo X pushes the same memory-expansion idea into rack-scale AI fabrics where accelerator clusters need larger pools close to compute.

CXL, or Compute Express Link, lets systems attach DRAM and other memory over a PCIe-based bus while keeping cache coherency between devices and host processors.

That architecture can give servers access to memory beyond conventional motherboard limits, but the economics have changed as RDIMM prices rise and retired systems release large amounts of DDR4.

Leo 2 moves Astera’s E-series and P-series controllers from PCIe Gen5 and CXL 2.x to PCIe Gen6 and CXL 3.2.

The new PCIe generation doubles bandwidth per lane, which helps address one of the persistent trade-offs in CXL memory expansion: a server CPU has less aggregate PCIe and CXL bandwidth than native DRAM bandwidth.

The newer CXL layer also widens system-design options by enabling switch hierarchies, direct memory-to-memory paths and more than one expander hanging off the same processor port.

Astera also doubled the memory channels on each Leo 2 card, moving from two channels to four.

Each expander can be populated to 768GB with DDR4 or to 4TB with DDR5, giving customers separate paths for capacity and cost.

One DDR4 design uses four channels with three DIMMs per channel, allowing 12 DDR4 DIMMs on a single expander, a configuration the source describes as rare because of its complexity.

The DDR4 reuse pitch depends on reliability as much as price.

Older memory can be at least half a decade old, so Leo 2 adds resilience features meant to keep reused DIMMs in service.

A hardware test engine checks each DIMM with multiple patterns, and soft-ECC runs on top of DIMM hardware ECC to catch errors that pass the first layer.

The two Leo 2 lines keep different roles.

The E-series is built for memory expanders attached to a single host CPU.

The P-series is aimed at systems that share memory between two host CPUs, allowing a pool to be dynamically allocated instead of fixed to one processor.

Leo X is the larger shift.

Rather than attaching expansion memory through a host CPU, the controller connects Leo-based memory expanders to rack-scale fabric networks through Astera’s Scorpio PCIe switch chips.

That design lets AI accelerators reach the memory node more directly, including in scale-out domains outside a rack and tighter scale-up domains inside a node.

Astera is positioning Leo X around key-value cache capacity for AI inference.

Astera Labs reports that its own testing against a PCIe-based Nvidia H200 system found up to a 62% improvement in time to first token and a 22% improvement in overall token throughput.

Those are vendor test results, not independent benchmarks, and the source notes the comparison was not against a newer Blackwell-based system.

All three controllers are now available.

The commercial question is whether high DRAM prices, CXL 3.x server launches and AI memory pressure can turn memory expansion from a niche architecture into a practical purchasing option for hyperscalers and server vendors.