T-Head V900 Pushes Alibaba AI Chips Toward Full-Stack Infrastructure
TechNode reported that Alibaba chip subsidiary T-Head unveiled the Zhenwu V900 AI chip, a supernode server design and a Yitian CPU roadmap aimed at larger AI training and inference systems.

T-Head has pushed Alibaba’s chip ambitions beyond a single accelerator, TechNode reported, unveiling the Zhenwu V900 AI chip at the 2026 Apsara Conference in Hangzhou alongside a server and CPU roadmap built around larger training and inference systems.
The subsidiary introduced the V900 as its next high-end processor for AI computing workloads.
The part is designed for both training and inference.
The chipmaker is pairing it with interconnect, networking and storage components.
That system focus starts with the V900’s specifications.
T-Head claims the chip can reach triple the performance of the Zhenwu M890, its previous generation.
The processor also carries 216GB of memory, offers 1,200GB/s of inter-chip bandwidth and supports low-precision formats including FP8 and FP4.
Those figures point to the pressure created by larger models.
Extra memory can reduce the overhead of splitting models and moving data, while lower-precision formats can improve efficiency for suitable workloads.
T-Head presents the V900 as a system component for training and inference jobs that span multiple accelerators.
The proprietary ICN Switch interconnect is the next layer in that design.
Multiple V900 chips can be linked into supernodes with native memory semantics and unified memory addressing, allowing full-bandwidth connections across large groups of AI chips.
The company says a system can combine more than 1,000 V900 chips for tasks such as trillion-parameter model training and high-volume inference generated by AI agents.
Alibaba also showed a new-generation supernode server built around the V900 and three companion parts: the ICN Switch, the Panmai smart NIC and the Zhenyue SSD controller.
Together with Alibaba Cloud’s AI computing center network architecture, a single cluster using the chips is designed to scale to as many as 500,000 accelerators.
The approach builds on earlier deployments rather than starting from a blank slate.
Supernode servers based on the Zhenwu M890 are already in large-scale commercial deployment and support models with more than 2 trillion parameters, including Qwen3.8 and Kimi K3.
Zhenwu products have served more than 650 enterprise customers in sectors ranging from finance and autonomous driving to energy, manufacturing, embodied AI and large language models.
The roadmap also covers server CPUs.
The Yitian 720 and Yitian 730 server CPUs are scheduled for the third quarter of 2027.
T-Head claims one model is aimed at higher single-core performance, denser core counts and better power efficiency, while the Yitian 730 will use a T-Head-developed CPU microarchitecture with single-core SPECint2017/GHz performance of up to 1.4 times that of the Yitian 710.
The later Yitian 750 is expected to support T-Head’s proprietary ICN inter-chip protocol, letting the CPU connect directly with Zhenwu AI chips.
That roadmap makes the CPU part of the same infrastructure problem: as AI servers become more complex, coordination among compute, memory, network and data-access layers matters as much as individual processor claims.
Commercial timing remains a future test for the new chip.
T-Head expects the V900 to reach mass production and sales in the first quarter of 2027, and Alibaba Group CEO Wu Yongming linked higher annual AI chip shipments to wider adoption.
The broader portfolio reflects competition at the system level, where chip-to-chip communication and software integration are becoming central to AI infrastructure.




















