RISC-V Server Standards Move Toward First RVA23 Hardware

RISC-V’s push into data-centre hardware now depends less on whether the instruction set can be extended and more on whether its profiles can make different vendors’ chips behave predictably.

ServeTheHome covered SiFive’s Hot Chips 2026 presentation as the open architecture reaches its 16th year and moves toward first RVA23 server silicon expected this year.

The presentation treated standardisation as the bridge between a research-origin ISA and commercial systems.

RISC-V began at UC Berkeley, later gained a foundation and early commercial implementations, and is now being framed for server processors rather than only controllers or embedded cores.

SiFive’s core argument was that an open, community-developed standard can support many implementations without leaving software developers to guess which features are present.

That work is organised in layers.

SiFive’s presentation described basic instruction-set families for 32-bit and 64-bit designs, including reduced-register embedded variants; named extensions then add capabilities such as multiplication, vector processing, supervisor features or debug support.

Profiles sit above those pieces and define which combinations a class of hardware must carry.

Platform standards go one step wider by describing the surrounding machine, not only the processor core.

The profile layer is the data-centre hinge.

RVA is aimed at application processors that need mainstream software ecosystems, including Linux distributions and Android, while RVB23 serves application processors built around custom software stacks such as Yocto and OpenEmbedded.

RVA23, approved in October 2024, makes vector support and hypervisor capability part of the required baseline, giving operating-system and toolchain teams a firmer target than a custom ISA string.

Server requirements extend that baseline into the rest of the box.

The platform specification combines RVA23 processors with the RISC-V interrupt architecture and expected system interfaces including PCIe, IOMMU, UEFI, ACPI, TPM and common baseboard-management protocols.

SiFive presented that interface set as part of a complete server platform, extending the specification beyond the processor core.

AI workloads give the standard another deployment path.

The vector extension approved in 2021 provides 32 architectural vector registers, while its length-agnostic programming model lets software scale across implementations with very different datapath widths.

Matrix work remains more plural: SiFive described AME, IME and VME approaches, plus a vector-based fast path, leaving chip designers room to match matrix execution to their accelerator organisation.

The same presentation placed RISC-V across three AI roles.

It can act as a host processor, a device-side controller inside accelerators, or the main ISA for self-hosted edge AI and agentic CPU designs.

That breadth is the reason profile discipline matters; without a stable baseline, each successful implementation would risk becoming its own software island.

Security also moves through the architecture rather than arriving only as a platform add-on.

Physical-memory controls allow the highest privilege level to restrict code below it, Worlds adds isolation tags to bus transactions, and supervisor domains bring a page-table-based model for confidential-compute separation.

The security roadmap also includes cryptography, data-independent timing, control-flow integrity, pointer masking, CHERI, speculation controls, memory tagging and memory-encryption contexts.

At the base layer, SiFive listed four ratified ISAs—RV32I, RV64I, RV32E and RV64E—distinguished by address width and register count.

It also pointed to development work on a CHERI capability variant and future RV128 designs, while later Z-prefixed extensions group optional functions by category.

That roadmap shows why profiles must stabilize combinations before server vendors can target them.

SiFive’s rebuttal to fragmentation rested on comparison and reuse.

The presentation counted about 200 RISC-V extensions, against roughly twice that for AArch64 and about four times that for x86_64, while stressing that the same vector model can serve application cores, accelerators and embedded parts.

The first RVA23 servers will be the practical check on that claim: their arrival would turn a standards stack into a current route for RISC-V systems in AI and cloud infrastructure.