Rapidus Targets 2027 2nm Fab Ramp Without Volume Customer

Rapidus is counting on a fourfold capacity increase at a single fab in Hokkaido to establish Japan as a leading-edge chipmaking centre.

The Chitose facility is expected to start at roughly 6,000 wafer starts per month and reach about 25,000 within its first year of full-volume production.

But the company still has no publicly identified high-volume customer committed to the 2nm process that underpins the plan, Tom’s Hardware reported.

A fourfold ramp at one fab

The IIM-1 pilot line in Chitose began operating in April 2025, after the cleanroom was completed in 2024.

ASML delivered a TWINSCAN NXE:3800E in December 2024, Japan’s first mass-production-grade EUV scanner, and the tool completed its first exposure on April 1, 2025.

Rapidus is targeting mass production in the second half of fiscal 2027, followed by full-volume scaling in 2028.

Its business plan sets out an initial capacity of roughly 6,000 wafer starts per month and a ramp to around 25,000 within the first year.

The increase is intended to lower per-wafer costs, but the company’s entire production base remains concentrated in IIM-1.

The fab broke ground in September 2023 at Bibi in Chitose.

Its location provides water for wafer cleaning, a cooler climate that can reduce cooling loads and renewable-energy potential across wind, solar and hydro.

Local and prefectural authorities are supporting a “Hokkaido Valley” initiative spanning Tomakomai, Chitose and Ishikari.

The process and production model

Rapidus’s 2nm technology is a gate-all-around nanosheet design derived from IBM’s 2nm process, announced in 2021 after a partnership signed in December 2022.

More than 150 Rapidus engineers worked at IBM’s Albany NanoTech Complex in New York during 2023 and 2024, with about 80 later returning to Chitose to transfer and tune the process.

The company is also developing a manufacturing flow built around single-wafer front-end processing.

Its Rapid and Unified Manufacturing Service feeds per-wafer data into AI models that Rapidus says could accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung.

A 2nm Process Design Kit reached early customers in the first quarter of 2026, while the prototype achieved its expected electrical characteristics in July.

Rapidus has not published a yield figure.

The roadmap also includes chiplet and package design and manufacturing technology funded through NEDO’s approved fiscal 2026 budget, as well as longer-term panel-level glass-substrate packaging.

Government capital, private funding

Rapidus closed a ¥267.6 billion funding round in February.

The Japanese government contributed ¥100 billion through the Information-technology Promotion Agency, while 32 private companies supplied ¥167.6 billion.

Tokyo became the largest single shareholder and received a golden share granting veto power over major decisions, including share transfers and technology partnerships.

The Ministry of Trade and Industry added approximately ¥1 trillion across fiscal 2026 and 2027, bringing planned government backing to about ¥2.9 trillion.

A further ¥150 billion equity contribution in early June raised Rapidus’s combined capital and capital reserves to around ¥425 billion.

The state’s shares are largely non-voting, leaving its formal voting position near 11.5%.

If performance deteriorates, those shares can convert to a controlling stake of roughly 60%.

NEDO currently owns the fab buildings and equipment and leases them to Rapidus; planned public construction across fiscal 2027 and 2028 is intended to transfer those assets to the company as in-kind contributions in exchange for shares.

Customer demand and the rival capacity track

Chief executive Atsuyoshi Koike said in February that more than 60 companies were discussing 2nm capacity and that around 10 had received preliminary price quotations.

TrendForce reporting linked IBM and Canadian RISC-V accelerator startup Tenstorrent to those talks.

Fujitsu, a founding investor, is separately considering whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The signed design work is narrower than a volume allocation.

Tenstorrent’s 2023 agreement covers joint development of an edge-AI accelerator through a NEDO and Leading-edge Semiconductor Technology Center project.

Esperanto Technologies signed a separate cooperation memorandum in May 2024.

Neither arrangement represents the committed high-volume order Rapidus needs to fill a 25,000-wafer monthly ramp.

Japan’s other semiconductor track is TSMC’s JASM venture in Kumamoto.

Its first fab, backed by Sony, Denso and Toyota, began mass production in December 2024 on 12nm, 16nm, 22nm and 28nm nodes for automotive and industrial chips.

A second fab broke ground in 2025, with its planned node upgraded from 4nm to 3nm and production targeted around 2028.

Rapidus plans to begin 1.4nm development in 2026, start construction on a 1.4nm fab in 2027 and reach mass production around 2029.

Total lifetime investment is expected to exceed ¥7 trillion, including roughly ¥5 trillion to reach stable 2nm production.

The company posted a ¥375 million loss for fiscal 2025 and held ¥749.5 billion in total assets while seeking about ¥1 trillion from private investors.

Its targets of operating profitability around fiscal 2030 and an IPO in fiscal 2031 therefore depend on the 2027 ramp arriving on schedule and current customer discussions becoming committed wafer demand.