Intel 18A-P Enters Risk Production With Foundry Proof Still Pending
Intel Foundry says Intel 18A-P has entered risk production and brings performance, power and thermal gains over Intel 18A, but the update still leaves customer tape-outs and volume manufacturing undisclosed.
Intel Moves 18A-P To Risk Production
Intel Foundry said at the 2026 VLSI Symposium that Intel 18A-P, the performance-enhanced version of Intel 18A, has entered risk production.
The update gives customers and partners a process-roadmap milestone, not a finished volume-manufacturing result.
The company described Intel 18A-P as a design-rule-compatible extension of Intel 18A.
That matters for chip designers because existing IP and design flows can be reused more easily than they could on a more disruptive node shift.
Intel said the process keeps two cell heights of 180nm and 160nm and a contacted poly pitch of 50nm.
Intel's claimed gains are material but still need customer silicon evidence.
Intel said Intel 18A-P improves on Intel 18A by 9% at constant power or by 18% lower power at constant performance.
Intel also cited 20-40% better thermal resistance and 10-30% better via resistance through materials, geometry and design changes.
Power Boost Targets Frequency And Efficiency
The update included Power Boost, a dual-contact, low-resistance transistor option for Intel 18A-P. Intel said the option is intended to increase drive current and raise frequency at matched capacitance.
Intel also pointed to new low-power and high-performance transistor options and a fifth logic Vt pair between ULVT and LVT.
Those additions give designers more choices when they balance speed and power, while the public record still lacks named customers, chip products or tape-out schedules tied to the new options.
Naga Chandrasekaran, who leads Intel Foundry, framed the update as proof of long-term process commitment while acknowledging that more work remains ahead.
The foundry pitch rests on two technologies Intel says it brought to market last year with Intel 18A: gate-all-around transistors and backside power delivery.
Intel said at VLSI that measurements for those foundations showed 11% routed-area reduction and 10X dynamic-voltage-droop reduction versus a comparable frontside interconnect technology.
Intel said those results can enable up to 6% frequency uplift or more than 15% dynamic power reduction.
Intel also cited CPU-core test data for the same gate-all-around and backside-power foundation.
The company said frequency scaling improved at lower voltages, including about 30% frequency improvement at low voltage near 0.5V, while IR drop declined.
Scaling Research Points Beyond 18A
Intel also used the event to describe longer-range research.
One demonstration stacked NMOS and PMOS devices vertically in monolithic CFET inverters at a 45nm gate pitch, a possible route for logic scaling beyond gate-all-around transistors.
A separate research item covered gallium nitride power devices integrated on 300mm wafers with silicon logic, including a digital control block of roughly 1,000 gates.
Intel framed that work as a way to combine digital control and high-performance power devices in one process and reduce system complexity.
Interconnect research remains another constraint.
Intel said subtractive ruthenium with airgap integration achieved up to about 35% capacitance reduction and measurable frequency gains versus copper, pointing to one path for resistance-capacitance scaling as wiring shrinks.
Intel has given foundry customers a denser set of process claims around Intel 18A-P. The missing proof is commercial: Intel did not name customer tape-outs, production chip designs or a volume-manufacturing date beyond the risk-production milestone.
