Etched Raises $300 Million As $1 Billion Pre-Orders Test Inference Rack Plan

Inference-chip startup Etched now has funding and pre-order numbers large enough to move its rack plan beyond a lab demonstration, but the commercial proof still depends on shipments and public performance data.

EE Times reported that the San Jose company raised $300 million in a Series C round at a $10 billion pre-money valuation and already has $1 billion in pre-orders.

The round was led by Sequoia, with A16Z, Jane Street, SK Hynix, Diffusion Capital and existing investors participating.

The capital supports a vertically integrated AI hardware push that spans ASIC design, custom packaging, board design, cooling, servers and rack-level infrastructure.

Funding Round Comes With A Rack Shipment Plan

The pre-order book is the strongest disclosed demand signal.

During the San Jose visit, Etched president Robert Wachen put the buyer base among the largest AI companies and AI clusters, with hardware demand tied to coding, long-context agents, long-horizon agents and other inference-token workloads.

That demand is not yet deployed customer capacity.

The July 23 EE Times story placed Etched's current operating base in a San Jose cluster and lab and a newer Milpitas, California, R&D facility with a 10 MW data centre, a lab and a quick-turn SMT line.

Customer shipments are scheduled to begin this summer, turning the next phase into an installation and measurement test rather than another fundraising milestone.

The earlier product pitch was narrower: chips that hard-wire the transformer architecture into silicon and aim for token throughput an order of magnitude above Nvidia Blackwell-based systems.

The newer product case covers more inference patterns.

The design targets higher FLOPS and bandwidth for multi-trillion-parameter MoE models, diffusion models and state-space models.

Low-Voltage Inference Uses Under Half The Chip Voltage

The main technical mechanism is low-voltage inference, or LVI.

The company runs the transistors in its math engines at under half the voltage used by other AI chips, while leaving SRAM outside that low-voltage regime because standard SRAM cells cannot use sub-threshold operation today.

Wachen said the method lets Etched avoid thermal throttling and run at 80%+ utilisation for trillion-parameter MoE models.

He also placed current AI chip efficiency at 0.2 to 0.4 FLOPS delivered for every FLOPS purchased and projected that broad LVI use could double or triple inference capacity.

Those are company-owned performance claims; EE Times observed racks operating in prefill and decode configurations during a lab visit, but Etched declined to make benchmark figures public.

The technical caveat is physical rather than only architectural.

Low-voltage operation is usually restricted to small chips or crypto-mining ASICs because high current, current spikes and slower clock speeds are difficult to control.

The response spans fabrication, ASIC design, packaging, board, cooling and mechanical layers.

TSMC N4P And HBM Define The Supply Path

The chip is built on TSMC N4P and uses a full-reticle-sized design with six stacks of HBM.

The design uses a process node, packaging technology and memory path different from Nvidia's next-generation Rubin GPUs, making the Etched supply path separate from the Rubin supply chain.

Cluster memory is the other disclosed system-level piece.

Etched uses a low-latency shared memory pool across a whole cluster in a single scale-up domain, with a custom high-bandwidth interconnect for access to SRAM and HBM across chips.

The San Jose lab separates the prefill and decode stages across different racks, a configuration aimed at inference workflows that split context loading from token generation.

The reported pre-order book is $1 billion, while the team has grown beyond 450 people.

The company has not named rack customers or published benchmark methodology, leaving shipments to determine whether the pre-order book turns into deployed inference capacity.